Abstract: This paper proposes a novel 10-GS/s 7-bit time-interleaved time-domain Successive Approximation Register (SAR) Analog-To-Digital Converter (ADC) that utilizes a speed-enhanced bootstrapped ...
Abstract: This paper presents two fully standard-cell-based synthesizable Successive Approximation Register Analog-to-Digital Converters (SAR ADCs) and the automated layout generation framework. The ...
Some results have been hidden because they may be inaccessible to you
Show inaccessible results
Feedback