EDN

Design for test boot camp, part 1: Scan test

My colleagues from Mentor Graphics, Ron Press, Martin Keim, and I often write about various aspects of digital IC test. If you started following the Test Voices blog when it was part of Test & ...
Semiconductor Engineering

Hyperconvergence Of Design For Test And Physical Design

In today’s highly competitive semiconductor industry, chip-design companies strive for competitive advantages by optimizing designs for PPA (Power, Performance, Area). Along with the functional logic, ...
EDN

Design for test boot camp, part 4: Built-in self-test

Logic built-in self-test (LBIST), is a mechanism that lets an (IC) test the integrity of its own digital logic structures. LBIST operates by stimulating the logic-based operations of the IC and then ...
Electronic Design

What’s Next for Physically Aware DFT?

Why isolated flows negatively impact design schedule and PPA. Benefits of unified DFT, synthesis, and physical design flows. Physical implementation optimization methods for test compression and scan ...